The present invention relates to a semiconductor device having complementary metal oxide semiconductor field effect transistor (hereinafter referred to as CMOS) devices and in particular to a BiCMOS type semiconductor device having CMOS transistors and bipolar transistors. A term "CMOS transistor" or "MOSFET" used herein is not limited to a transistor having an oxide layer as a gate insulating layer and includes a transistor having a nitride layer or a multilayer structure of a nitride layer and an oxide layer.
Bipolar devices have a high drive ability and a high mutual conductance (gm) whereas CMOS devices have a low power consumption and a high integration degree. Hence, BiCMOS devices including bipolar devices and fine CMOS devices monolithically formed, which operate at fast speed and a low power consumption have been developed. Semiconductor devices having CMOS transistors and bipolar transistors on one and the same semiconductor substrate is described in an article "Bipolar CMOS RAM which is becoming influential in fast and high integrated memories", NIKKEI ELECTRONICS, published by NIKKEI BP Co., Ltd., Mar. 10, 1986, pp. 199-217 and in an article "Hi-BiCMOS technology which has realized 64KSRAM", Denshi Zairyo,, Published by Kohgyo Chosakai, June 1986, pp. 75-79.
These articles describe that high performance BiCMOS devices which operate at fast speed and lower power consumption and provide basic circuits having excellent performances, which cannot be obtained solely by either of bipolar and CMOS transistors, are manufactured by forming bipolar and CMOS transistors in a basic logical circuit in a composite manner. The latter article describes the dependency of device characteristic on process parameters and illustrates the impurity concentration distribution of n- and p-wells and the sectional structure of an NMOS and the expansion of a depletion layer. The latter article also describes that the disclosed devices have a feature that a buried well structure provides a low impurity concentration region between a surface shallow well which controls the threshold voltage of the MOS transistor and a buried layer.
A technology for controlling the threshold voltage of a buried channel type PMOS transistor in which the surface of the n-well is made of p-type if n-type polycrystal silicon is used for a gate electrode is described in "Submicron Devices I: Electronics Material series" published by Maruzen Co., Ltd. pp. 152-170.
Japanese Unexamined Patent Publication JP-A-2-72661 (published Mar. 12, 1990) discloses that channel regions of PMOS transistors are double injected so that the breakdown voltage across source and drain of the PMOS transistors is enhanced and the threshold voltage is controlled.
High performance Bi-CMOS devices have excellent various features such as multi-performances, high integration degree, low power consumption and high drive ability.
A high-BiCMOS device having these features which is shown in, for example, FIG. 1 may be considered although it is not publicly known.
Referring now to FIG. 1, a p type MOSFET Q.sub.1, an n type MOSFET Q.sub.2, a bipolar transistor Q.sub.3 are formed on one and the same p type semiconductor substrate. A plurality of n+ type diffusion layers (not two layers are illustrated in the drawing) and p+ type diffusion layers (only one layer is illustrated in the drawing) are formed in different regions on the main surface of a semiconductor substrate 1. The n type wells 4 and 4' which have the same conductivity type as the n.sup.+ type diffusion layer 2 are formed thereon and a p type well 5 having the same conductivity type as the p.sup.+ type diffusion layer 3 is provided thereon. An oxide layer (local oxidation of silicon "LOCOS" oxide layer) 6 is selectively formed on the n type wells 4, 4' and a p type well 5 by a LOCOS process.
In FIG. 1, two n type wells 4 and 4' are provided adjacent to the p type well 5 on the opposite sides thereof. The NMOS transistor Q.sub.2 is provided on the p type well 5 and the bipolar transistor Q.sub.3 is formed on the n type well 4'. The PMOS transistor Q.sub.1 is formed on the n type well 4.
The bipolar transistor Q.sub.3 comprises a p- type base region 7 formed in the surface portion of the n type well 4', an n+ type emitter region 8 formed in the surface portion of a part of the base region 7, an n.sup.+ type collector leading diffusion layer 9 separated from the base region 7 and extending from the surface of the device to the lower n.sup.+ type diffusion layer 2 and a p.sup.+ type outer base region 10 formed in a part of the base region 7.
The PMOS transistor Q.sub.1 is formed in the n type well 4 and comprises p.sup.+ type source and drain regions 15 and 16 formed on the surface portion of the n type well 4 and a gate insulating layer (gate oxide layer) 17 on the n type well between the source and drain regions 15 and 16. A gate electrode 18 formed of a polysilicon layer is provided on the gate insulating layer 17.
The NMOS transistor Q.sub.2 comprises n.sup.+ type source and drain regions 25 and 26 on the surface portion of the p type well 5 and a gate insulating layer (oxide layer) 27 on the surface of the p type well 5 between the source and drain regions 25 and 26. A gate electrode 28 is provided on the gate insulating layer 27.
The gate electrodes 18 and 28 of the PMOS and NMOS transistors Q.sub.1 and Q.sub.2 are formed of an n type polysilicon and both gate insulation layers 17 and 27 are formed of a silicon oxide layer. The surface of the device between the elements is covered with a thick LOCOS oxide layer (silicon oxide layer) 6. Spacers covering the sides of the gate electrodes and emitter electrodes are omitted in the drawing for simplicity of illustration.
The CMOS device having the above mentioned structure includes the n.sup.+ type diffusion layer 2 and the p.sup.+ type diffusion layer 3 having a higher concentration of each impurity buried bellow the n type wells 4 and 4' and the p type well 5, resulting in a reduction of a parastic collector series resistance, an increase in isolation breakdown voltage between buried collectors themselves and an enhancement of immunity for a latch-up between PMOS and NMOS transistors.
Furthermore, in such a CMOS structure, p type impurity layer 14P1 is formed in the surface portion of the n type well 4 under the gate insulating layer 17 of the PMOS transistors Q.sub.1 for the purpose of controlling the threshold voltage of the PMOS transistor. A p type impurity layer 14P2 is similarly formed in the surface portion of the p type well 5 under the gate insulating layer 27 of the NMOS transistor.
FIG. 2 is a graph showing the impurity concentration distribution in a depth direction under the gate insulating layer 17 of the PMOS transistor Q.sub.1. FIG. 3 is a graph showing the impurity concentration distribution in a thicknesswise direction under the gate insulating layer 27 of the NMOS transistor Q.sub.2. It is apparent from both FIGS. 2 and 3 that the concentration distributions of the transistors Q.sub.1 and Q.sub.2 are determined by the impurity concentrations N.sub.Q1W and N.sub.Q2W of the wells having opposite conductivity types of the source and drain and the impurity concentrations N.sub.Q1P and N.sub.Q2P of the p type surface impurity layers 14P1 and 14P2. That is, the p type impurity layer 14P1 is formed for the purpose of controlling the threshold voltage of the PMOS transistor, resulting in that the concentration N.sub.Q1P of the p type impurity in the vicinity of the gate insulating layer of the PMOS transistor Q.sub.1 is selected so that it is less thin the concentration N.sub.Q1W of the n type impurity forming the well. Both of peak values of the impurity concentrations N.sub.Q1P and N.sub.Q2P of the p type surface impurity layers 14P1 and 14P2 of the PMOS and NMOS transistors Q.sub.1 and Q.sub.2 are about 1.times.10.sup.17 cm.sup.-3. The impurity concentration at the interface between the impurity concentration N.sub.Q1P of the p type impurity layer 14P1 and the impurity concentration N.sub.Q1W of the n type well 4 in the PMOS transistor Q.sub.1 of the FIG. 2 is about 2.times.10.sup.16 cm.sup.-3 while the impurity concentration at the interface between the impurity concentration N.sub.Q2 of the p type laver 14P2 and impurity concentration N.sub.Q2W of the p type well 5 in the NMOS transistor Q.sub.2 of FIG. 3 is about 4.times.10.sup.16 cm.sup.-3.
The BiCMOS device having such a structure shown in FIG. 1 is manufactured through steps as shown in FIGS. 4A through 4C.
Firstly, a p.sup.- type semiconductor substrate 1 is prepared as shown in FIG. 4A. Thereafter a desired number of n+ and p+ type diffusion layers 2 and 3 having a high impurity concentration are formed in separate regions on the main surface of the p type semiconductor substrate. In this case, the p.sup.+ type diffusion layer 3 is provided in the center of the drawing and the n.sup.+ type diffusion layers 2 are disposed on the opposite sides of the p.sup.+ type diffusion layer 3.
Then, an epitaxial growth processing is performed to deposit an epitaxial grown layer on the main surface of the p type semiconductor substrate 1 as shown in FIG. 4B. The n type wells 4 and 4' having the same conductivity as that of the underlying diffusion layer 2 are formed by injecting phosphorus into those portion of the epitaxial layer which are on the layers 2, while a p type well 5 having the same conductivity as the underlying diffusion layer 3 is formed by injecting boron or BF.sub.2 into that portion of the epitacial layer which is on the layer 3.
The thick oxide layer (LOCOS oxide layer) is then formed for isolating elements and thereafter p type impurity layers 14P1, 14P2 and 14P3 and a gate insulating layer 17 (27) are formed as shown in FIG. 4C.
Thereafter, each of elements such as the bipolar transistor Q3, the PMOS transistor Q1 and NMOS transistor Q2 are formed on respective regions. That is, the base region 7, the emitter region 8, the collector leading diffusion layer 9 and the outer base 10 are formed in the right n type well 4 and the gate insulating layer 27, the gate electrode 28, the source region 25 and the drain region 26 are formed in the central p type well 5 and a gate insulating layer 17, the gate electrode 18, the source region 15 and the drain region 16 are formed in the left n type well 4.